In a known way, and as shown schematically in FIG. 1, a non-volatile memory device, designated by 1, for example, of a flash type or of the PCM (Phase-Change Memory) type, in general comprises a memory array 2 made up of a plurality of memory cells 3, arranged in rows (wordlines WL) and columns (bitlines BL).
Each memory cell 3 is constituted by a storage element, for example, formed by a floating-gate transistor in flash memories, with its gate terminal designed to be coupled to a respective wordline WL, a first conduction terminal designed to be coupled to a respective bitline BL, and a second conduction terminal connected to a reference potential (for example, ground, GND). In particular, the gate terminals of the memory cells 3 of a same wordline WL are connected together.
A column-decoder circuit 4 and a row-decoder circuit 5 enable selection, on the basis of address signals received at input (generated in a per se known manner and designated as a whole by AS), of the memory cells 3, and in particular the corresponding wordlines WL and bitlines BL, each time addressed, enabling biasing thereof to appropriate voltage and current values during the memory operations.
The column-decoder circuit 4 defines in particular a reading path, designed to create a conductive path between the bitlines BL of the memory array 2 each time selected, and a sense-amplifier circuit 10, designed to compare the current circulating in the addressed memory cell 3 with a reference current in order to determine the datum stored.